The present invention relates to a sense amplifier circuit that senses and amplifies the potential difference between a pair of bit lines connected to a semiconductor memory.
FIG. 1 shows a conventional main circuit for a dynamic random access memory (DRAM). As the figure indicates, there are a plurality of memory cells M1, M2, and so on, in a memory cell array 1 of a DRAM. Each memory cell has the same structure consisting of a parallel-plate capacitor 3 and an N-channel type metal oxide-silicon semiconductor (NMOS) device 2. One electrode of the capacitor 3 is connected to the source electrode of the NMOS device 2, while the other electrode of the capacitor is connected to a first reference potential VCP, which is the cell plate potential. The drain and gate electrodes of the NMOS device 2 in memory cell M1 are connected to a bit line BL and a word line WL0, respectively. The drain and gate electrodes of the NMOS device 7 in memory cell M2 are connected to a bit line BLB and a word line WL1, respectively.
The bit lines BL and BLB that are supplied to the memory cell array 1 are connected to an equalizing circuit 4. The equalizing circuit 4 is used to supply the same potential level on the bit lines BL and BLB, and consists of two NMOS devices 4a and 4b, the source electrodes of which are connected to a second reference potential VBL for the purpose of pre-charging the bit lines. The drain electrodes of the NMOS devices 4a and 4b are connected to the bit lines BL and BLB, respectively, while the gate electrodes (i.e., of the NMOS devices 4a and 4b) receive a control signal EQM. The level of the first reference potential VCP and second potential VBL is halfway between a first power potential VSS and a second power potential VCC. The VCP and VBL are generated by a VCP generating circuit 5 and a VBL generating circuit 6, respectively.
A sense circuit 10 is connected to the bit lines BL and BLB. In the sense circuit, the bit lines BL and BLB are connected to sense amplifier nodes NA and NAB by NMOS devices 11 and 12, respectively, which are transfer gates. Further, the gate electrodes of the NMOS devices 11 and 12 receive a control signal TG. When the control signal TG becomes active, the NMOS devices 11 and 12 are turned on. Consequently, the nodes NA and NAB become connected to the bit lines BL and BLB through NMOS devices 11 and 12, respectively.
Between the nodes NA and NAB is a sense amplifier 13 that consists of two P-channel type metal oxide silicon semiconductor (PMOS) devices 13a and 13b, the source electrodes of which are connected to each other. Further, between the node NA and node NAB is connected a second sense amplifier 14 that consists of NMOS 14a and 14b, the source electrodes of which are connected to each other. The node NA is connected to the drain electrodes of the PMOS device 13a and NMOS devices 14a, and to the gate electrodes of the PMOS device 13b and NMOS device 14b. The node NAB is connected to the drain electrodes of the PMOS device 13b and NMOS device 14b, and to the gate electrodes of the PMOS device 13a and NMOS device 14a.
The source electrodes of the PMOS device 13a and 13b are connected to the drain electrode of the PMOS device 15, the source electrode of which is connected to the second power potential VCC. The source electrodes of the NMOS device 14a and 14b are connected to the drain electrode of the NMOS device 16, the source electrode of which is connected to the first power potential VSS. The gate electrode of the NMOS device 16 receives connected to a sense amplifier activating signal SLNG, which is the output signal of an inverter 17, the input of which is a sense starting signal SLNGB. The gate electrode of the PMOS device 15 receives another sense amplifier activating signal SLPG, which is the output signal of an inverter 18, the input of which is the sense signal SLNG. The power and ground supplies of both inverters (17 and 18) are connected to the second power potential VCC and to the first power potential VSS, respectively, so that the output signal levels (of inverters 17 and 18) are either VCC or VSS, depending on the input signal level.
In an actual DRAM, a plurality of bit line pairs are supplied to a memory cell array 1. Accordingly, a plurality of sense circuits 10 are connected to corresponding bit line pairs. The PMOS device 15, the NMOS device 16, and the inverters 17 and 18, however, can be shared by several sense circuits.
FIG. 2 shows a waveform diagram illustrating the operation of the circuit in FIG. 1. The operation of a conventional DRAM will now be described with reference to FIG. 2.
When the control signal EQM falls from "H" level to "L" level, the NMOS devices 4a and 4b in the equalizing circuit 4 are turned off, and the bit lines BL and BLB are disconnected from the second reference potential VBL. When the potential level of the word line WL0 reaches a higher potential level (VCC+Vt(threshold voltage of the NMOS device 2 in memory cell M1)+a(operation margin of the NMOS device 2 in memory cell M1)), a small potential difference caused by memory cell data is provided to the bit lines BL and BLB. In addition, when the potential level of the word line WL0 reaches a higher potential level (VCC+Vt+a), the control signal TG also rises up to (VCC+Vt+a). This in turn activates the NMOS devices 11 and 12, and the bit lines BL and BLB become connected to the nodes NA and NAB, respectively.
The sense operation starts when the sense starting signal SLNGB falls from "H" level to "L" level. When the sense starting signal SLNGB drops to "L", the inverter 17 causes the sense amplifier activating signal SLNG to rise from "L" level to "H" level (VCC), and the sense amplifier activating signal SLPG falls from "H" level to "L" level (VSS). Therefore, both the PMOS device 15 and the NMOS device 16 are turned on and the sense amplifiers 13 and 14 are activated. The small potential difference between the nodes NA and NAB connected to the bit lines BL and BLB is sensed and amplified by the just-activated sense amplifiers 13 and 14 by charging and discharging the nodes NA and NAB through the PMOS device 15 and NMOS device 16, respectively.
There exists, however, the following problem in a conventional DRAM circuit. When the sense circuit 10 operates (i.e., when it senses and amplifies), power noise is generated by the charging and discharging current on the bit lines BL and BLB. Moreover, a voltage drop in the power supply occurs due to the parasitic resistance of the power supply wirings that provide the power potentials VSS and VCC to the NMOS device 16 and the PMOS device 15, respectively. The power noise reduces the operating margin of peripheral circuits.